In dynamic RAMs (DRAMs) a bit pair develops a voltage differential which is amplified by a sense amplifier. A selected bit line pair is coupled to a data line pair where amplification also occurs. A secondary amplifier which is coupled to the data line pair is also coupled to an output buffer for providing the output of the DRAM. The speed with which the secondary amplifier can resolve data provided thereto directly affects the access time of the DRAM. The speed of the secondary sense amplifier is directly affected by its gain. The data lines have in the past been precharged at or near VDD, the power supply voltage of about 5 volts. This was effective in establishing a predetermined voltage against which a convenient voltage differential could be driven. Particularly in view of the difficulty that a sense amplifier has in sourcing current, a sense amplifier is much more effective in sinking current. Consequently, a larger voltage differential could be established by only requiring the sense amplifier to sink current to establish the voltage differential on the data lines. This was effective but did not maximize the usage of the gain potential of the secondary amplifier.